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ChipX, the Structured ASIC Leader | Home
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Structured ASICs are a category of custom devices that approach the performance of today's Standard Cell ASICs, while dramatically simplifying the design complexity and project risk. Structured ASICs offer designers a set of devices with specific, customizable metal layers along with predefined metal layers, which can contain the underlying pattern of logic cells, memory, and I/O. By virtue of the predefined structures, the ASIC vendor can design any time-consuming task – such as test, signal integrity and IR drop – into the architecture.
Structured ASICs simplify the complexity of custom silicon design by providing a fabric of identical building block cells that are prearranged in a series of sizes and complexities. The design task involves mapping the design into a "blank slate" of silicon by choosing from a large library of building block cells, and interconnecting them as necessary. Only the top layers need be customized, allowing the design to benefit from faster turnaround time and reduced complexity as well as more favorable NRE. By choosing 2, 3, or 4 customizable metal layers, the designer is in complete control of the trade-off between density, cycle time, and mask complexity.
Gate Arrays, the ancestor of Structured ASICs, consists simply of an array of gates in the pre-defined layers of metal. This leads to congestion when routing more complex designs and a great deal of unused silicon. Structured ASICs address this problem by using logic cells to achieve maximum local flexibility, density and higher performance. Also, Gate Arrays typically do not include hard IP such as memory, processors, analog cores and physical layer components. Structured ASICs lend themselves easily to IP inclusion, tuning the surrounding fabric to accommodate each specific hard IP element.
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